1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, a design method, a design apparatus, and a program, and particularly to a technology for designing a semiconductor integrated circuit device so as to prevent breakdown or degradation due to a charge-up phenomenon in manufacturing steps thereof.
2. Description of the Related Art
In manufacturing steps of a semiconductor integrated circuit, a plasma or ion beam technique is used. In such steps, when wiring of the semiconductor integrated circuit is coupled to a gate electrode, charges are accumulated in the wiring. If the accumulated charges exceed a given amount, the breakdown or degradation of a gate oxide film is caused thereby, or the performance of a transistor is degraded thereby. Such a phenomenon is called an antenna effect.
To prevent damage to the gate oxide film due to charge-up resulting from the antenna effect, it is commonly practiced during the design of the semiconductor integrated circuit to limit, in accordance with the area or capacitance of the gate, the area of wiring directly coupled to the gate or the perimeter thereof reduced to the area, and thereby take anti-charge-up measures.
As a semiconductor device process has been increasingly miniaturized, the influence of not only the area of wiring but also a layout in the vicinity of the wiring increases to make it difficult to obtain a semiconductor integrated circuit which is sufficiently stable against the antenna effect. This causes the need to perform design with a certain degree of allowance for an antenna ratio, which is a ratio between the area of the wiring and the area of a gate electrode. As a result, the area of wiring directly coupled to the gate is limited more than necessary. In other words, this results in frequent use of the insertion of a repeater cell or a diode cell in the wiring, the adjustment of the size of a transistor to achieve a wiring/gate area of not less than a predetermined value in an uppermost wiring layer, the use of a cell to which a new transistor is added, or the like to increase cases where a chip size cannot be sufficiently reduced.
A technique is disclosed in Japanese Application Publication No. 2006-128498 which also considers, as an example of such influence of a layout in the vicinity of wiring, the influence of charge-up via an inter-line capacitance between wires adjacent to the wiring directly coupled to the gate or the like, and designs/manufactures a semiconductor integrated circuit device.
In Japanese Application Publication No. 2006-140349, a design method is disclosed in which an antenna value, which is an estimated value of damage to a transistor gate, is outputted based on an antenna ratio and a variation rate of plasma charging damage due to a layout in the vicinity of the transistor gate. More specifically, it is described that, in an antenna value calculation step, the antenna value is calculated based on the antenna ratio in consideration of the effect of reducing an antenna effect depending on whether a diffusion layer coupled to the other terminal of wiring directly coupled to the transistor gate forms a diode or a substrate contact. It is further described that the antenna value calculation step includes the step of calculating the antenna value by considering a variation component based on the effect of reducing the antenna effect, which is in accordance with the area of the diffusion layer coupled to the transistor gate via the wiring against the antenna effect and so forth.